Surface Mountable Packages
Leadless Ceramic SMT Packages and Chip Carriers with PCTF® for a Direct PCB Mount
|Commercial Quasi-Hermetic SMT Package||Fully Hermetic SMT Package|
Leadless SMT packages and chip carriers design concept is based on creating an interconnect pattern on a ceramic substrate with PCTF® (Plated Copper on Thick Film Technology) for multiple or single die applications. Essential features of this package design are solid plugged via holes and wraparounds (castellations) which are described below.
PLATED THROUGH HOLES, SOLID VIAS and CASTELLATIONS
Solid Metal Vias provide hermetic, high thermal and electrical conductivity connections.
- Plugged vias withstand gross leak test requirements common for commercial and industrial applications.
- For more demanding applications, plugged vias are fabricated to meet full MIL STD hermeticity requirements and pass fine leak test to 10-8 atm cc/sec.
|Ceramic thickness||Plugged Via Holes|
|.010” – .025”||.007” – .020”|
|.025” – .040”||.009” – .030”|
|.040” +||Consult Factory|
Wraparounds (Castellations) provide cost effective, reliable SMT leadless connection for a direct PCB mounting in a wide ceramic size range, to a 1×1” ceramic substrate and larger. Standard Dimensions for Solid Plugged Via and Plated Castellation are listed below.
Ceramic Thickness – A
Castellation Width – B
Castellation Depth – C
Metallization Width – D
Plated Through Hole
Solid Plugged Via
Plated Copper Through Holes ensure a higher current carrying capacity, low loss RF signal and ground interconnections.
Solid plugged via holes are fully hermetic, withstand gross and fine leak test (10-8 atm cc/s).
Plugged via holes provide excellent thermal and electrical signal and ground interconnections.
Plated Castellations / Wraparound provide for a reliable direct PCB attach / for SMT chip carriers and packages.
Efficient Thermal Management
Plugged vias with High thermal conductivity of 200 W/°CxM create an effective heat transfer path with a low thermal resistance.
- Via fill material thermal conductivity is actually better than 200 W/°C xM.
- Typical .008”-.012” plugged via in .015″ – .020” thick alumina ceramic will create a thermal pass with a thermal resistance of ~ 35-40de
- °C/W per via depending on Cu plating thickness, substrate thickness and plugged via hole diameter.
- A single die of 3mm x 3mm (.120”x.120”) dissipating 5 W has 20 plugged vias underneath the chip. Approximately, the total effective thermal resistance θ of 0.020” thick alumina under the die is 2°C/W. Therefore, the temperature rise should not exceed more than: ∆T=10° C max (from the back of a die to the back of the package).
SMT LEDLESS HEMETIC PACKAGE: SPECIAL LAYOUT DESIGN CONSIDERATIONS
Hermeticity of a package is achieved by ensuring the hermeticity of both plugged via holes and hermetic sealing of ring frame to ceramic substrate.
1. Ring Frame Landing Area Width
Due to the necessity to ensure a proper solder fillet form the inner and outer sides of the ring frame the minimum dimensions required for solder fillets are listed below:
- Standard: Minimum X.=.010” from each side
- Premium: Minimum X’=.008” from each side
Following the above mentioned rule the landing area for the Ring Frame is calculated as follows:
|Add||Ring Frame Wall Thickness|
|Add||Fillet width on both sides (2X or 2X’)|
|Min Width of the Ring Frame landing area|
2. Plugged Via Metalization Diameter
To ensure the hermeticity a minimum annular ring around the circumference of the plugged via hole should be as listed below:
- Standard: .010” from each side Minimum
- Premium: .008” from each side Minimum
Following the above mentioned rule the annular ring dimensions for the plugged via hole must be calculated as follows:
|Nominal diameter of the drilled hole|
|10% of the ceramic thickness|
|Annular ring width * 2|
|Min Diameter of the Annular Ring|
Notes: More information is available
- For packages Sizes and availability consult factory
- For Reliability Testing report consult factory
- Packages operate in a broad frequency range. Consult factory for the details